In semiconductor device manufacturing, three-dimensional (3D) integration can be achieved, for instance, using through-substrate vias (TSVs) for chip stacking. Connecting vias between the first metal (for instance copper) layer and the contact layer is one useful method for achieving such integration, especially for 20 nm technology and beyond. There is a desire to achieve minimum pitch and minimum Critical Dimension (CD) for these connecting vias to create as many possible connections between the contact and first metal layers. Current practices for forming tightly packed connecting vias uses two reticles in a double pattern process, in order to achieve the desired points of connectivity between the metal and TSV layers.
What is needed is a better facility for providing resolution enhancement for increased via connection coverage in semiconductor devices. One particularly useful application for this is in maximizing via connection coverage area on top of through-substrate vias (TSVs) of a semiconductor device.